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Course/Workshop: Multi-threaded Programming, Tuning and Optimization on Multi-core MPP Platforms


The HP2C platform announces a 2-day intensive course focused on multi-threaded programming, tuning and optimization and multi-threaded libraries on massively parallel processing (MPP) systems that are composed of multi-core processors.  The course syllabus is below and it will be delivered by senior personnel from Cray, Roberto Ansaloni (Cray Italy) and Adrian Tate (Technical Lead of Math Software, Cray), and CSCS (Sadaf Alam and Neil Stringfellow).

Registration deadline: November 20, 2010. 

Please contact alam(at)cscs.ch for further technical information and apinna(at)cscs.ch for logistical information.



Roberto Ansaloni and Adrian Tate from Cray; Sadaf Alam and Neil Stringfellow from CSCS

VenueEPFL, Room MA B1 486,  http://plan.epfl.ch
Time9:00 - 17:00 both days

CSCS advanced development system called Palu, a Cray XE6 MPP system, which is composed on dual-socket AMD Magny-cours Opteron processors (24 cores per node) and a high performance interconnect called GEMINI will be targeted for the hands-on sessions. Participants are expected to be familiar with basic concepts of parallel programming specifically MPI and OpenMP programming.  Please refer to the online training material available at:


Maximum number of participants25
Target audienceThis course is specifically aimed at HP2C users.

Participants are kindly requested to make their own arrangements for accommodation. Herein find some suggestions:

Starling Hotel , Route Cantonale 31, 1025 Saint-Sulpice
Tel: +41 (0)21 694 85 85, starlinghotels-lausanne.com

Hotel Regina, 18, rue Grand St. Jean, 1003 Lausanne
Tel: +41 (0)21 320 24 41, www.hotel-regina.ch

Hotel des Voyageurs, Rue Grand St Jean 19, 1003 Lausanne
Tel: +41 (0)21 319 91 11 , www.voyageurs.ch

Hotel Agora, Avenue Rond Point 9, 1006 Lausanne
Tel: +41 (0)21 55 55 9 55, fhotels.ch/fassbind-hotels.ch/en-hotel-agora.html

Motel Les Pierrettes, Route Cantonale 19, 1025 Saint-Sulpice
Tel: +41 (0)21 691 25 25, www.motel-suisse.com

Course Syllabus

Day One (9.00 to 17.00 hrs):

1.      Historical perspective
        - Evolution of multi-core processors
        - Parallel computing
        - Programming and parallel programming
        - OpenMP and MPI standardization
2.      MPP systems with multi-core processors
        - Building blocks of an MPP system
        - Characteristic features of multi-core based MPP systems
        - Introduction to Cray XE6 system
3.      Parallel programming with MPI and OpenMP
        - MPI programming fundamentals
        - OpenMP programming fundamentals
        - OpenMP parallel constructs
        - Hybrid (MPI + OpenMP) programming considerations, opportunities and challenges
4.      Exploiting Cray Programming Environment for hybrid applications
        - Details on code development environment
        - Availability and usage of program execution environment
        - Task and thread mapping strategy and supporting tools
5.      LAB (hands-on)
        - Experiments with threaded codes
        - Executing a hybrid code
        - Experimenting with compiler and run-time options on XE6 platform
6.      Discussion on hybrid programming best practices and misconceptions
        - Results and analysis of hybrid test cases
        - Identifying load balance and overhead
        - Introduction to hyperthreading

Day Two (9.00 to 17.00 hrs):

1.      Introduction to multi-threaded libraries
        - Historical perspective
        - Auto-tuning approach on Cray MPP systems
        - Examples: performance benefits of auto-tuned libraries
        - Evolution of threaded libraries
2.      LAB
        - Experiments using libraries on the Cray XE6 platform
3.      Advanced libraries concepts
        - Runtime options
        - Hybrid mode libraries
        - Discussion on programming and execution parameters
4.      LAB
        - Hybrid mode library usage experiments
5.      Performance measurement and tuning
        - Performance tools for threaded and hybrid applications
        - Measurement and analysis considerations
        - Identification of performance issues and bottlenecks
        - Tunable parameters
6.      LAB
        - Experiments with performance tools
7.      Future systems  and programming models
       - Next generation multi-core processors
       - MPP systems with accelerators
       - Hybrid programming for accelerator based MPP systems
       - Programming models interoperability
       - Code and performance portability considerations
       - Libraries development for future systems

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