Event Detail


Cray XT5 Code-Porting Workshop


Registration and Hotel Reservations close June 15th 2009!!

Registration for this Course is Free!!

The Swiss National Supercomputing Centre (CSCS) is pleased to announce, in association with the Partnership for Advanced Computing in Europe (PRACE), a three-day Cray XT5 code porting workshop. The workshop will be held from the 13th – 15th July, 2009 at CSCS, Manno and will consist of a series of lectures and “hands-ons” sessions covering fundamental through advanced code optimization and porting techniques. The workshop is open to participants from all PRACE Member countries.
Registration for this course is Free.

All participants will be staying at the International au Lac in Downtown Lugano.
Please make your reservation with the hotel when you register for this course.
The hotels contact details are as follows: info@hotel-international.chThis e-mail address is being protected from spam bots, you need JavaScript enabled to view it or you can contact them by phone +41 (0)91 922 7541 and mention CSCS workshop as your reference.

Transport is provided to take participants to and from CSCS and the hotel.

Requirements: A laptop with ssh software installed eg. putty client etc.

Click here to see the video of the course.


• John Levesque – Director, Cray Supercomputing Center of Excellence

   Luiz DeRose - Cray Supercomputing Center of Excellence
• Roberto Ansaloni – Cray Inc, Italy



Day 1 9:30am - 10:30amI. Architecture of the AMD Quad Core 
a. Architectural features that the application developer needs to know
  • i. Functional Units
  • ii. Cache Architecture
  • iii. Memory interface

b. Issues using Quad core node in XT5 MPP

10:30am - 10:45amBreak
10:45am -
11:30 am
2. Compiler considerations when using the Quad Core
a. Vectorization to use SSE instructions
b. Memory pre-fetching
c. How to use shared memory parallelization in the compiler
11:30am - 12:15am3. Using Craypat to profile applications on the XT5
12:15pm - 14:00pmLunch
14:00pm - 16:30pmAssignment – obtain profiles of your application running on the XT5
Day 2 9:00am - 10:30am4. Optimizations for the AMD Quad Core
a. Optimization techniques that the application developer needs to know
i. Vectorization
ii. Blocking for cache
iii. Using prefetch directives
10:30am - 10:45amBreak 
10:45am - 11:45am5. Using Apprentice to examine hardware counters for understanding cache utilization and vectorization
11:45am - 13:30pmLunch 
13:30pm - 16:30pmAssignment – optimize your application for node performance 
Social Event
Day 3 9:00am - 10:30am6. Message Passing Optimizations for the XT5
a. Optimization techniques that the application developer needs to know
  • i. Pre-posting messages
  • ii. MPI environment variables
10:30am - 10:45amBreak 
10:45am - 11:45amTechnical Presentation - Joost VandeVondele 
11:45am - 12:45am7. Using Apprentice to examine MPI performance 
12:45am - 14:30pmLunch 
14:30pm - 16:00pmAssignment – optimize your application for MPI performance 

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