Event Detail


Algorithmic RE-Engineering



  • Teodoro Laino (IBM Research, Zurich Research Laboratory)
  • Alessandro Curioni (IBM Research, Zurich Research Laboratory)



Algorithmic Re-Engineering for Modern Non-Conventional Processing Units

Within the next few years, supercomputers will achieve access to and even overcome the petascale limit, rendering them several orders of magnitude more powerful than the fastest supercomputer available today.
Despite the promise of almost unimaginable computing power, however, even computing experts wonder whether this time the hardware developers have raced too far ahead of many programmers' ability to create software. As a result, although breakthroughs across science and engineering are anticipated with this incredible computational resources few researchers are prepared to utilze this massive computing capability.
The reason for this delay is that applications software development has always been driven by the hardware developments. Ever since the commodity cluster became a feasible alternative to the big supercomputing facilities, the hardware industry ceased to release any innovative concepts at the level of micro-processing unit, focusing more on boosting CPU performance. Nonetherless, it was clear that driving the clock speeds and straight-line instruction throughput even higher was not sustainable in the long term due to technological limitations. That is why the major processor manufactures have turned en masse to a series of different approaches like hyper-threading units, hybrid architectures and special purpose hardware, genereally identified as concurrent architectures. This means essentially that the "free lunch" for software developments has come to an end as the need for hardware-optimized algorithmic solutions will play an ever-increasing role in the fututre in attaining and overcoming the next order of magnitude: the long awaited milestone of 1 Petaflop/s, which was realised in June 2008 with the IBM machine Roadrunner.


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